Semiconductor storage technology is one of key technologies in the field of microelectronics technology. As focus of information technology turns from networks and computers to storage, research of storage technology becomes an important direction of information technology research. Current research of storage technology mainly focuses on high-density and high-performance non-volatile flash technology. As device sizes continuously decrease, conventional FLASH technology encounters great difficulties during size scaling, such as crosstalk and low writing speed, etc. As a result, the conventional FLASH technology cannot satisfy requirements of storage technology development of post-20 nm-node. New storage technology is required for high-capacity storage.
Recently, resistive storage technology has attracted attention of many researchers, and has been considered as a key technology of post-20 nm-node. A resistive random access memory utilizes reversible conversions between a high-resistance state and a low-resistance state of storage medium under control of an electrical signal to distinguish two states, as a conventional RRAM does. Alternatively, the two states can also be implemented by resistance change caused by phase change of material under the electrical signal, as a conventional PRAM does. A resistive cell typically comprises a top electrode, a resistive (phase-change) material, and a bottom electrode, which are stacked in sequence. Such a structure has many advantages because it is simple, easy to be manufactured, and compatible with existing CMOS processes. Therefore, three-dimensional integration of resistive cells may facilitate high-density data storage and may be applied in various applications such as Solid State Disk.
Conventional resistive storage technology needs diodes or selection transistors in implementing cell selection, as a 1D1R structure or a 1T1R structure does. A three-dimensional resistive storage is mainly a three-dimensional integration of the two typical storage structures. 1D1R-type three-dimensional resistive memory devices can improve storage density to a certain degree. However, because the diode in the resistive cell typically comprises a PN junction, substantial scaling of resistive cell height is difficult. Meanwhile, during manufacturing of a multi-stack resistive cell, a high temperature is required in an implantation process and a subsequent dopant activation process in forming the PN junction, causing pre-formed cell performance to be affected by later manufacturing processes. This is disadvantageous for reliable operation of the memory device. Therefore, 1T1R-type three-dimensional storage technology exhibits more potential in high-density integration.
FIG. 1 shows a cross-sectional view along a bit-line direction of a 1T1R-type three-dimensional memory structure proposed by the applicant. FIG. 2 shows a cross-sectional view along a word-line direction of the 1T1R-type three-dimensional memory structure proposed by the applicant. As shown in FIG. 1 and FIG. 2, as an example, each vertical storage string comprises a transistor and four resistive cells. This structure achieves high-density integration in comparison with planar-type flash cells and planar-type resistive cells. However, with the emergence of ultra-high-capacity (>Tera-bit) storage requirement, the structure shown in FIG. 1 encounters great processing challenges in integration of more layers of resistive cells, and thus has difficulties in satisfying the requirement. The resistive cells as shown in FIG. 1 share a common pillar-shape bottom electrode, which is formed by via etching process. The via has an etching depth that is determined by respective thicknesses of layers constituting each resistive cell and a number of the resistive cells. Assuming that the top electrode of the resistive cell has a thickness of 50 nm, and the cells are separated vertically by a space of 50 nm, each resistive cell will be formed with a thickness of 50 nm.
FIG. 3 shows, according to prior art, a comparison between a stack height obtained when the via has a bottom diameter of 30 nm and that obtained when the via has a bottom diameter of 0 nm. The via has a top diameter of 100 nm and an etching angle of 85 degree. As shown in FIG. 3, when the etching angle is 85 degree, only 4˜5 layers of resistive cells can be integrated in a stack. Even though an etching angle of 88 degree can be achieved by improving etching process, 14 layers of resistive cells can be integrated at most. Meanwhile, because reduction of bottom diameter of the via will cause the resistance of the bottom electrode to dramatically increase and hollow holes will be easily created in small vias, which will cause open circuit, an actual number of layers of resistive cells that can be integrated are less than the above estimated ones.
Therefore, in the process of manufacturing the three-dimensional semiconductor memory device, the existing etching process cannot achieve a big ratio between depth and diameter of the via, which is a great obstacle of high-density longitudinal integration of three-dimensional resistive (phase-change) cells.